With the continued scaling of the channel length of MOSFETs (Metal Oxide Field-effect Transistors), a series of effects, which are ignorable in a long-channel MOSFET, are becoming more and more significant and are even becoming a dominant factor in affecting performance These effects are collectively referred to as the short-channel effects. The short-channel effects tend to deteriorate the electrical performance of a device, for example, causing the problems of reducing the threshold voltage of a gate, increasing the power consumption, reducing the signal to noise ratio, etc.
In order to control the short-channel effects, more impurity elements (such as phosphorus, boron, etc.) have to be doped into a channel, but this tends to lead to the reduced carrier mobility in the channel of the device. Moreover, there is a problem that it is difficult to control the distribution abruptness of the impurities doped into the channel, which tends to cause severe short-channel effects. The traditional SiGe PMOS strained silicon technology also encounters bottleneck problems, making it difficult to provide stronger strain for the channel. Furthermore, in aspects of the thickness of a gate oxide dielectric, there is also a bottleneck problem that it is difficult for the speed of reducing the gate oxide thickness to keep pace with that of reducing the gate width, and the leakage current in the gate dielectric becomes larger and larger. In addition, the critical dimensions are decreasing continuously, causing the resistance of the source/drain regions to increase continuously and the power consumption of the device to become higher and higher.
Currently, the dominant thinking in the industry is to improve the traditional planar device technology, trying to reduce the thickness of the channel region and to eliminate the electrical neutral layer under the depletion layer in the channel so that the depletion layer in the channel can fill up the whole channel region, which is the so-called fully depleted (FD) device while the traditional planar devices belong to the partially depleted (PD) devices.
However, in order to fabricate the fully depleted device, an extremely thin thickness of the channel silicon layer is required. The traditional manufacturing process, particularly the traditional bulk silicon-based manufacturing process, has difficulties in fabricating a structure meeting such requirements, or the costs are high. Even for the newly developed SOI (Silicon-On-Insulator) process, it is still difficult to control the thickness of the channel silicon layer at a relatively thin level. Regarding how to realize the fully depleted device, the focus of R&D efforts is turning to a 3-dimensional device structure, i.e., to a fully depleted dual-gate or tri-gate technology.
The 3-dimensional device structure (also referred to as a vertical device in some documents) refers to a device structure in which the cross section of the source/drain region and that of the gate are not in the same plane, which substantially belongs to a FinFet (Fin Field-effect Transistor) structure.
After turning to the 3-dimensional device structure, the channel region is no longer contained in the bulk silicon or SOI, and rather, it becomes independent from these structures. Therefore, the fully depleted channel with extremely thin thickness can be fabricated by means of etching, etc.
FIG. 1 shows a 3D semiconductor device which has been proposed, the semiconductor device comprising: a semiconductor substrate 20 that is located on an insulating layer 10; source and drain regions 30 abutting first opposite sides 22 of the semiconductor substrate 20; gates 40 that are located on second sides 24 of the semiconductor substrate 20, which are adjacent to the first sides 22 (a gate dielectric layer and a work function metal layer sandwiched between the gates 40 and the semiconductor substrate 20 are not shown in the figure). In this case, in order to reduce the resistances of the source and drain regions, the edge of the source and drain regions 30 may be expanded, i.e., the width of the source or drain region 30 (along the xx′ direction) is larger than the thickness of the semiconductor substrate 20. Therefore, with the increase of the width (d) of the source and drain regions 30, the parasitic capacitances between the source or drain region 30 and the gate 40, and between the source or drain region 30 and the semiconductor substrate 20 increase, thus increasing the resistance-capacitance delay or decreasing the alternative current performance of the device.